MOS silicon gate technology defines an MOS transistor location by a field oxide opening, and defines the MOS channel region location by a polysilicon gate electrode overlying this opening. The width of the polysilicon (poly) determines the channel length L, and the width of the field oxide opening determines the channel width W. The poly is made longer than the channel width to allow for misalignment tolerance. For a very narrow sub micron channel width this tolerance can be almost as large as the width. Furthermore, if a metal connection is to be made to the poly, the poly has to extend even further beyond the channel width to make room for a contact hole to the metal, severely limiting layout density.
Another fundamental problem with silicon gate technology arises from the fact that the polysilicon is used for a first layer interconnect as well as defining the MOS gate electrodes. This means that polysilicon cannot be patterned to freely cross over a diffusion without also creating an MOS transistor at the cross over location.
Yet another fundamental problem with silicon gate technology is that the channel length L is determined by the poly width, which width is determined by the width of radiation patterned photoresist. To produce ever faster circuits, it is desirable to make L as short as possible; however, it becomes very difficult to pattern photoresist line widths to be less than 100 nm.